XiPU uROM Generator
urom.cpp
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1 /*
2  * Author: Pawel Jablonski
3  * E-mail: pj@xirx.net
4  * WWW: xirx.net
5  * GIT: git.xirx.net
6  *
7  * License: You can use this code however you like
8  * but leave information about the original author.
9  * Code is free for non-commercial and commercial use.
10  */
11 
12 #include "urom.h"
13 
14 //! Default constructor for creating an uROM. Generating a full instrution set.
16 {
17  Instruction instruction;
18 
19  // LOAD_I + RPC+1 // ======================================================
20 
21  // NOP
22  // Fill whole instruction table as default
23  for(unsigned int i = 0; i < URomData::INSTRUCTION_QUANTITY; i++)
24  {
25  instruction = Instruction(0b00000000);
28  this->uRomData.addInstruction(instruction);
29  }
30 
31  // LOAD_I + RPC // ========================================================
32 
33  // HALT
34  instruction = Instruction(0b11111111);
37  this->uRomData.addInstruction(instruction);
38 
39  // LOAD_I + STORE + RPC+1 // ==============================================
40 
41  // LDF reg
42  instruction = Instruction(0b00000100, Instruction::Arg::ABXY);
46  this->uRomData.addInstruction(instruction);
47 
48  // LDR reg
49  instruction = Instruction(0b00001000, Instruction::Arg::ABXY);
53  this->uRomData.addInstruction(instruction);
54 
55  // STR reg
56  instruction = Instruction(0b00001100, Instruction::Arg::ABXY);
60  this->uRomData.addInstruction(instruction);
61 
62  // MOV reg, reg
63  instruction = Instruction(0b10000000, Instruction::Arg::ABXY, Instruction::Arg::ABXY);
67  this->uRomData.addInstruction(instruction);
68 
69  // IN reg
70  instruction = Instruction(0b00010000, Instruction::Arg::ABXY);
74  this->uRomData.addInstruction(instruction);
75 
76  // OUT reg
77  instruction = Instruction(0b00010100, Instruction::Arg::ABXY);
81  this->uRomData.addInstruction(instruction);
82 
83  // LOAD_I + ALU + RPC+1 // ================================================
84 
85  // CMP reg, reg
86  instruction = Instruction(0b11100000, Instruction::Arg::AB, Instruction::Arg::ABXY);
90  this->uRomData.addInstruction(instruction);
91 
92  // LOAD_I + ALU + STORE + RPC+1 // ========================================
93 
94  // INC reg
95  instruction = Instruction(0b00011000, Instruction::Arg::ABXY);
100  this->uRomData.addInstruction(instruction);
101 
102  // INCC reg
108  this->uRomData.addInstruction(instruction);
109 
115  this->uRomData.addInstruction(instruction);
116 
117  // DEC reg
118  instruction = Instruction(0b00011100, Instruction::Arg::ABXY);
123  this->uRomData.addInstruction(instruction);
124 
125  // DECC reg
131  this->uRomData.addInstruction(instruction);
132 
138  this->uRomData.addInstruction(instruction);
139 
140  // NOT reg
141  instruction = Instruction(0b00100000, Instruction::Arg::ABXY);
146  this->uRomData.addInstruction(instruction);
147 
148  // ADD reg, reg
149  instruction = Instruction(0b10010000, Instruction::Arg::AB, Instruction::Arg::ABXY);
154  this->uRomData.addInstruction(instruction);
155 
156  // ADDC reg, reg
162  this->uRomData.addInstruction(instruction);
163 
169  this->uRomData.addInstruction(instruction);
170 
171  // SUB reg, reg
172  instruction = Instruction(0b10100000, Instruction::Arg::AB, Instruction::Arg::ABXY);
177  this->uRomData.addInstruction(instruction);
178 
179  // SUBC reg, reg
185  this->uRomData.addInstruction(instruction);
186 
192  this->uRomData.addInstruction(instruction);
193 
194  // AND reg, reg
195  instruction = Instruction(0b10110000, Instruction::Arg::AB, Instruction::Arg::ABXY);
200  this->uRomData.addInstruction(instruction);
201 
202  // OR reg, reg
203  instruction = Instruction(0b10111000, Instruction::Arg::AB, Instruction::Arg::ABXY);
208  this->uRomData.addInstruction(instruction);
209 
210  // XOR reg, reg
211  instruction = Instruction(0b11000000, Instruction::Arg::AB, Instruction::Arg::ABXY);
216  this->uRomData.addInstruction(instruction);
217 
218  // SHL reg
219  instruction = Instruction(0b01111000, Instruction::Arg::ABXY);
224  this->uRomData.addInstruction(instruction);
225 
226  // CLR reg
227  instruction = Instruction(0b11001000, Instruction::Arg::ABXY);
232  this->uRomData.addInstruction(instruction);
233 
234  // LOAD_I + 8x ALU + STORE + RPC+1 // =====================================
235 
236  // SHR reg
249  this->uRomData.addInstruction(instruction);
250 
263  this->uRomData.addInstruction(instruction);
264 
265  // SWAP reg
278  this->uRomData.addInstruction(instruction);
279 
292  this->uRomData.addInstruction(instruction);
293 
294  // LOAD_I + PC+1 + STORE + RPC+1 // =======================================
295 
296  // MOV val, reg
297  instruction = Instruction(0b00100100, Instruction::Arg::Val256, Instruction::Arg::ABXY);
302  this->uRomData.addInstruction(instruction);
303 
304  // OUT val
305  instruction = Instruction(0b00000010, Instruction::Arg::Val256);
310  this->uRomData.addInstruction(instruction);
311 
312  // LOAD_I + PC+1 + LOAD_D + STORE + RPC+1 // ===============================
313 
314  // STR val
315  instruction = Instruction(0b00000001, Instruction::Arg::Val256);
321  this->uRomData.addInstruction(instruction);
322 
323  // LOAD_I + PC+1 + LOAD_D + ALU + RPC+1 // ================================
324 
325  // CMP val, reg
326  instruction = Instruction(0b00101000, Instruction::Arg::Val256, Instruction::Arg::ABXY);
332  this->uRomData.addInstruction(instruction);
333 
334  // LOAD_I + PC+1 + LOAD_D + ALU + STORE + RPC+1 // ========================
335 
336  // ADD val, reg
337  instruction = Instruction(0b00101100, Instruction::Arg::Val256, Instruction::Arg::ABXY);
344  this->uRomData.addInstruction(instruction);
345 
346  // ADDC val, reg
351  instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b1001, false, false));
354  this->uRomData.addInstruction(instruction);
355 
363  this->uRomData.addInstruction(instruction);
364 
365  // SUB val, reg
366  instruction = Instruction(0b00110100, Instruction::Arg::Val256, Instruction::Arg::ABXY);
370  instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b0110, false, false));
373  this->uRomData.addInstruction(instruction);
374 
375  // SUBC val, reg
380  instruction.addStep(Step(Step::BusAR::ABXY, Step::BusAW::ALU_T, Step::BusB::D, Step::BusC::Default, 0b0110, false, false));
383  this->uRomData.addInstruction(instruction);
384 
392  this->uRomData.addInstruction(instruction);
393 
394  // AND val, reg
395  instruction = Instruction(0b00111100, Instruction::Arg::Val256, Instruction::Arg::ABXY);
402  this->uRomData.addInstruction(instruction);
403 
404  // OR val, reg
405  instruction = Instruction(0b01000000, Instruction::Arg::Val256, Instruction::Arg::ABXY);
412  this->uRomData.addInstruction(instruction);
413 
414  // XOR val, reg
415  instruction = Instruction(0b01000100, Instruction::Arg::Val256, Instruction::Arg::ABXY);
422  this->uRomData.addInstruction(instruction);
423 
424  // LOAD_I + PC+1 + LOAD_MAL + PC+1 + LOAD_MAH + STORE + RPC+1 // ==========
425 
426  // LDF addr, reg
427  instruction = Instruction(0b01011000, Instruction::Arg::Addr, Instruction::Arg::ABXY);
435  this->uRomData.addInstruction(instruction);
436 
437  // LDR addr, reg
438  instruction = Instruction(0b01011100, Instruction::Arg::Addr, Instruction::Arg::ABXY);
446  this->uRomData.addInstruction(instruction);
447 
448  // STR reg, addr
449  instruction = Instruction(0b01100000, Instruction::Arg::ABXY, Instruction::Arg::Addr);
457  this->uRomData.addInstruction(instruction);
458 
459  // LOAD_I + PC+1 + LOAD_D + PC+1 + LOAD_MAL + PC+1 + LOAD_MAH + STORE + RPC+1 //
460 
461  // STR val, addr
462  instruction = Instruction(0b00000011, Instruction::Arg::Val256, Instruction::Arg::Addr);
472  this->uRomData.addInstruction(instruction);
473 
474  // LOAD_I + LOAD + LOAD + RPC+1 + LOAD_I + LOAD + RPC+1 // ================
475 
476  // XCHG reg, reg
477  instruction = Instruction(0b11010000, Instruction::Arg::ABXY, Instruction::Arg::ABXY);
482  this->uRomData.addInstruction(instruction);
483 
484  instruction = Instruction(0b11001100, Instruction::Arg::ABXY);
488  this->uRomData.addInstruction(instruction);
489 
490  // LOAD_I + PC+1 + LOAD_MAL + PC+1 + LOAD_MAH + 3x STORE + RPC+1 // =======
491 
492  // XCHG addr, reg
493  instruction = Instruction(0b01001000, Instruction::Arg::Addr, Instruction::Arg::ABXY);
503  this->uRomData.addInstruction(instruction);
504 
505  // LOAD_I + PC+1 + LOAD_PCL + PC+1 + LOAD_PCH + STORE + RESET // ============
506 
507  // JMP addr
508  instruction = Instruction(0b11110000, Instruction::Arg::Addr);
516  this->uRomData.addInstruction(instruction);
517 
518  // LOAD_I + PC+1 + LOAD_D + PC+1 + LOAD_PCH + STORE + RESET // ============
519  // + PC+1 + PC+1 + RPC+1 // ========================================
520 
521  // JE addr
522  for(int c = 0; c < 2; c++)
523  {
524  for(int z = 0; z < 2; z++)
525  {
528 
529  instruction = Instruction(0b11111000, Instruction::Arg::Addr, Instruction::Arg::None, Instruction::Arg::None, cFlag, zFlag);
530 
531  if(c & z)
532  {
540  }
541  else
542  {
547  }
548 
549  this->uRomData.addInstruction(instruction);
550  }
551  }
552 
553  // JNE addr
554  for(int c = 0; c < 2; c++)
555  {
556  for(int z = 0; z < 2; z++)
557  {
560 
561  instruction = Instruction(0b11111001, Instruction::Arg::Addr, Instruction::Arg::None, Instruction::Arg::None, cFlag, zFlag);
562 
563  if(!(c & z))
564  {
572  }
573  else
574  {
579  }
580 
581  this->uRomData.addInstruction(instruction);
582  }
583  }
584 
585  // JG addr
586  for(int c = 0; c < 2; c++)
587  {
588  for(int z = 0; z < 2; z++)
589  {
592 
593  instruction = Instruction(0b11111010, Instruction::Arg::Addr, Instruction::Arg::None, Instruction::Arg::None, cFlag, zFlag);
594 
595  if(c & !z)
596  {
604  }
605  else
606  {
611  }
612 
613  this->uRomData.addInstruction(instruction);
614  }
615  }
616 
617  // JGE addr
618  for(int c = 0; c < 2; c++)
619  {
620  for(int z = 0; z < 2; z++)
621  {
624 
625  instruction = Instruction(0b11111011, Instruction::Arg::Addr, Instruction::Arg::None, Instruction::Arg::None, cFlag, zFlag);
626 
627  if(c)
628  {
636  }
637  else
638  {
643  }
644 
645  this->uRomData.addInstruction(instruction);
646  }
647  }
648 
649  // JL addr
650  for(int c = 0; c < 2; c++)
651  {
652  for(int z = 0; z < 2; z++)
653  {
656 
657  instruction = Instruction(0b11111100, Instruction::Arg::Addr, Instruction::Arg::None, Instruction::Arg::None, cFlag, zFlag);
658 
659  if(!c & !z)
660  {
668  }
669  else
670  {
675  }
676 
677  this->uRomData.addInstruction(instruction);
678  }
679  }
680 
681  // JLE addr
682  for(int c = 0; c < 2; c++)
683  {
684  for(int z = 0; z < 2; z++)
685  {
688 
689  instruction = Instruction(0b11111101, Instruction::Arg::Addr, Instruction::Arg::None, Instruction::Arg::None, cFlag, zFlag);
690 
691  if((!c & !z) || (c & z))
692  {
700  }
701  else
702  {
707  }
708 
709  this->uRomData.addInstruction(instruction);
710  }
711  }
712 
713  // LOAD_I + STORE + SP+1 + RPC+1 // =======================================
714 
715  // PUSH reg
716  instruction = Instruction(0b01100100, Instruction::Arg::ABXY);
721  this->uRomData.addInstruction(instruction);
722 
723  // LOAD_I + SP-1 + STORE + RPC+1 // =======================================
724 
725  // POP reg
726  instruction = Instruction(0b01101000, Instruction::Arg::ABXY);
731  this->uRomData.addInstruction(instruction);
732 
733  // LOAD_I + PC+1 + LOAD_D + PC+1 + LOAD_PCH + STORE + SP+1 + STORE + SP+1 + RESET //
734 
735  // CALL addr
736  instruction = Instruction(0b11110001, Instruction::Arg::Addr);
748  this->uRomData.addInstruction(instruction);
749 
750  // LOAD_I + SP-1 + STORE + SP-1 + STORE + RPC+1 // ========================
751 
752  // RET
753  instruction = Instruction(0b11110010);
760  this->uRomData.addInstruction(instruction);
761 
762  // LOAD_I + ALU + PC+1 + PC+1 + RPC+1 // ==================================
763  // + ALU + STORE + PC+1 + LOAD_D + PC+1 + LOAD_PCH + STORE + RESET //
764 
765  // LOOPE reg, reg, addr
766  for(int c = 0; c < 2; c++)
767  {
768  for(int z = 0; z < 2; z++)
769  {
772 
773  instruction = Instruction(0b11101000, Instruction::Arg::AB, Instruction::Arg::ABXY, Instruction::Arg::Addr, cFlag, zFlag);
776 
777  if(c & z)
778  {
782  }
783  else
784  {
788  }
789 
795  this->uRomData.addInstruction(instruction);
796  }
797  }
798 
799  // LOAD_I + ALU + STORE + PC+1 + PC+1 + PC+1 + RPC+1 // ===================
800  // + ALU + STORE + PC+1 + LOAD_D + PC+1 + LOAD_PCH + STORE + RESET //
801 
802  // LOOPE val, reg, addr
803  for(int c = 0; c < 2; c++)
804  {
805  for(int z = 0; z < 2; z++)
806  {
809 
810  instruction = Instruction(0b01001100, Instruction::Arg::Val256, Instruction::Arg::ABXY, Instruction::Arg::Addr, cFlag, zFlag);
815 
816  if(c & z)
817  {
821  }
822  else
823  {
824 
828  }
829 
835  this->uRomData.addInstruction(instruction);
836  }
837  }
838 
839  // LOAD_I + ALU STORE + PC+1 + PC+1 + RPC+1 // ============================
840  // + ALU + STORE + PC+1 + LOAD_D + PC+1 + LOAD_PCH + STORE + RESET //
841 
842  // LOOPZ reg, addr
843  for(int c = 0; c < 2; c++)
844  {
845  for(int z = 0; z < 2; z++)
846  {
849 
850  instruction = Instruction(0b11110100, Instruction::Arg::ABXY, Instruction::Arg::Addr, Instruction::Arg::None, cFlag, zFlag);
853  instruction.addStep(Step(Step::BusAR::T, Step::BusAW::D));
855 
856  if(c & z)
857  {
861  }
862  else
863  {
864 
868  }
869 
875 
876  this->uRomData.addInstruction(instruction);
877  }
878  }
879 }
880 
881 /**
882  * Save a binary microcode to files
883  *
884  * @param urom0Path Path to the first output file
885  * @param urom1Path Path to the second output file
886  *
887  * @return Status of the save operation
888  */
889 bool URom::saveFiles(const QString &urom0Path, const QString &urom1Path)
890 {
891  // Try to save the data to the output files
892  return(this->uRomData.saveFiles(urom0Path, urom1Path));
893 }
This class contains atomic steps for the control unit of defined instruction.
Definition: instruction.h:21
Flag
Tristate flag definition for carry and zero control bits.
Definition: instruction.h:35
@ Enable
Only accept the enable value.
@ Disable
Only accept the disable value.
@ ABXY
Main and auxiliary registers.
@ Addr
16 bit unsigned address
@ None
No argument.
@ AB
Only main registers.
@ Val256
8 bit unsigned value
void addStep(const Step &step)
Definition: instruction.cpp:54
Definition: step.h:24
@ ABXY
Main and auxiliary registers.
@ MAH
Memory Address High register.
@ ALU_T
ALU operation.
@ RPC
Reset Program Counter.
@ PCH
Program Counter High register.
@ SP_PLUS
Increse Stack Pointer.
@ MAL
Memory Address Low register.
@ PC_PLUS
Increse Program Counter.
@ RPC_PLUS
Reset the step counter and increse Program Counter.
@ I
Instruction register.
@ Ram
RAM access.
@ SP_MINUS
Decrese Stack Pointer.
@ OUT
Output register.
@ PCL
Program Counter Low register.
@ D
Hidden data register.
@ AB
Main registers.
@ D
Hidden data register.
@ ABXY
Main and auxiliary registers.
@ PCH
Program Counter High register.
@ T
ALU temp register.
@ Flash
FLASH access.
@ IN
Input register.
@ Ram
RAM access.
@ PCL
Program Counter Low register.
@ D
Hidden data register.
@ MA
Full 16 bit Memory Address register.
@ SP
Full 16 bit Stack Pointer register.
@ XY
Full 16 bit auxiliary register.
static const int INSTRUCTION_QUANTITY
Support only for 256 opcodes.
Definition: uromdata.h:25
bool saveFiles(const QString &urom0Path, const QString &urom1Path)
Definition: uromdata.cpp:82
void addInstruction(const Instruction &instruction)
Definition: uromdata.cpp:26
URomData uRomData
uROM data with an opcode table
Definition: urom.h:28
URom()
Default constructor for creating an uROM. Generating a full instrution set.
Definition: urom.cpp:15
bool saveFiles(const QString &urom0Path, const QString &urom1Path)
Definition: urom.cpp:889