XiPU - Design of the uROM
Description of how the uROM works and what it is. It contains an explanation of every signal generated by the uROM and how instructions are decoded.
1. uROM
Every CPU has a set of instructions described by built-in microcode inside it. In XiPU the microcode is named uROM because it is implemented by using EEPROM chips for steering data lines, registers, and ALU.
All assembler instructions are split into fundamental steps, where every step sets BUSes in a predefined state described in uROM. Each assembler instruction can have a maximum of 16 microsteps.
A special counter starts incrementing itself from zero when the next instruction to execute is loaded. Every instruction has an end microstep reset procedure for that counter. The counter and quantity of the microsteps are reasons why some instructions execute in 2-3 cycles of the XiPU and the more complicated ones need more cycles to be executed.
2. Implementation
The uROM uses two EEPROMs to store microsteps. To every EEPROM are connected an Instruction Register, a 4-bit microstep counter, Carry and Zero Flags. The last bit of the address is not used.
The uROM has 16 selection lines for steering the other modules of the XiPU. Some signals are connected directly to other components, and the rest use multiplexers to steer more status lines, which cannot be used simultaneously.
2.1. Selection lines connected to the uROM chip 0
Pin | Name | Description |
---|---|---|
0-2 | BUS AR bit 0-2 | Select a register on BUS A to read. List of possible sources: 0x0 : ABXY - Main and auxiliary registers |
3-6 | BUS AW bit 0-3 | Select a register on BUS A to write. List of possible destinations: 0x0 : None - Not selected |
7 | BUS B | Select a register on BUS B to read. List of possible sources: 0x0 : AB - Main registers |
2.2. Selection lines connected to the uROM chip 1
Pin | Name | Description |
---|---|---|
0-1 | BUS C bit 0-1 | Select a register on BUS C to address memory. List of possible sources: 0x0 : PC - Full 16 bit Program Counter register |
2-5 | ALU S bit 0-3 | Select an operation for ALU in arithmetic mode. List of possible operations: 0x0 : Out = In_A + C 0x0 : Out = NOT In_A |
6 | ALU M | Select arithmetic or logic mode for ALU |
7 | ALU C | Carry flag for ALU |
2.3. Register selection
When the instruction uses a register or registers, the exact register used as source or destination is part of the instruction opcode. Based on that information, the Control Unit can select the correct register or registers for every microstep.
It generates a specific limitation in the design of the XiPU. It is not possible to use more than two registers in one instruction, and it is not possible to write more than one register in one instruction. This is why the "xchg" instruction needed to use two opcodes.
3. Generating uROM
uROM generator is a special piece of software created to generate binary files needed to write to EEPROM chips located on the XiPU board.
It is a very useful tool to automate the problematic process of creating new binary images. To add a new instruction or modify an existing one, you only need to update the source code of the uROM generator where microcode is defined. It is much easier to work with simple definitions made in C++ than manually editing the binary files.
To generate uROM files, please type:
This command will generate two uROM binary files for the EEPROM #0 and #1.