XiPU - Design of the XiPU
Description of the XiPU design. Explanation of what every part of the processor does, why it is needed, and what its function is. It also contains a list of parts needed to build the XiPU.
1. Modules
The XiPU Board is made using a 4-layer PCB. The two internal layers are used for VCC and GND purposes. The size is equal to the A4 paper format.
The board contains only the strictly needed parts for the working logic of the processor. It contains 2 EEPROM chips with the uCode needed for the Control Unit and 1 EEPROM with the OS. It contains 2 SRAM chips too.
The only non-logic part on the board is the IO BUS connector needed to communicate with the IO Board.
1.1. Clock
The basic frequency of the clock is 2 MHz. The frequency is divided by 2 to get two clock signals that are phase shifted, and the effective speed of the XiPU is 1 MHz.
The reset signal is raised after the supply is stabilized. It uses two MCP100-475DI to generate the POWER_OK and RESET_OK signals.
The Step Counter is used to select a step of the current instruction. It is a 4-bit counter, and it resets after executed each instruction.
1.2. Control Unit
The Counter Unit based on 2 EEPROMs with the uROM. It uses the value stored in the I Register, the Step Counter and the C Flag to select the current status for all 3 data buses. It controls the flow of the whole processor.
The I Register contains the current executing opcode. Every instruction step at the beginning has loaded an opcode from memory based on the Program Counter value in that register. This register latches the opcode until the next instruction is executed.
1.3. ROM and RAM
The XiPU has 32 KB of EEPROM for the OS and 64 KB of SRAM. It has two address methods, one for accessing the FLASH space and the other for getting access to the RAM space. The lower half of the memory is separated, but the higher half of FLASH is mapped to the RAM space, making it available to load an application and execute it.
1.4. Program Counter
The Program Counter is a 16-bit register that stores the current address of the executing instruction, or payload of that instruction. It could be incremented or set using another value.
1.5. Stack Pointer
Stack Pointer is a 16-bit register where the higher 8 bits are fixed and it in practice allow to access only to 256 bytes of RAM. It could be only incremented or decremented and is not possible to read od write the value of that register.
1.6. Main Registers
The XiPU has 2 Main Registers for all-purpose operations. They are the A and B Registers. They could be used in all instructions as a source or destination.
1.7. Auxiliary Registers
The XiPU has 2 Auxiliary Registers. They are the X and Y Registers. They could be used in most instructions, with some exceptions. It could be used as a 16-bit address register Y:X for reading or writing data to the memory.
1.8. Hidden Data Register
The Hidden Data Register is the D Register. It is used as an internal data buffer during the execution of an instruction. It is not possible to get access to it from the code.
1.9. Hidden Address Register
The Hidden Address Register is the MA Register, and it is a 16-bit one. It is used to address a memory during the execution of an instruction. It is not possible to get access to it from the code.
1.10. Arithmetic and Logic Unit
The Arithmetic and Logic Unit is built using 2 connected 74181 chips. It allows calculating basic arithmetic and logic operations using two 8-bit arguments.
The Temporary ALU Output Register is the T Register. It is used to store the output from the ALU and use it in the next step of executing the instruction.
The Flags Register contains 2 flags. The first one is the Carry flag and the second is the Zero flag. Both of them are needed to support ALU arithmetic and resolve conditions for branching jumps.
1.11. IO BUS
The IO BUS Input is an 8-bit register needed to read the incoming data from the IO Board to the XiPU.
The IO BUS Output is an 8-bit register needed to write data to send to the IO Board.
2. List of parts
| # | Name | Quantity | Description |
|---|---|---|---|
| 1. | XiPU PCB | 1 | |
| 2. | 5k Ohm THT | 1 | Resistor |
| 3. | 5.1k Ohm THT | 2 | Resistor |
| 4. | 1M Ohm THT | 1 | Resistor |
| 5. | 33 pF THT | 2 | Capacitor |
| 6. | 100 nF THT | 2 | Capacitor |
| 7. | 2 MHz 16-30pF HC49/U | 1 | Quartz |
| 8. | 74HCT04 | 2 | Hex inverter gate |
| 9. | 74HCT08 | 3 | Quad 2-input AND gate |
| 10. | 74HCT32 | 5 | Quad 2-input OR gate |
| 11. | 74HCT107 | 1 | Dual J-K flip-flop, clear |
| 12. | 74HCT138 | 1 | 3-to-8 line decoder/demultiplexer, inverting outputs |
| 13. | 74HCT139 | 3 | Dual 2-to-4 line decoder/demultiplexer, inverting outputs |
| 14. | 74HCT154 | 1 | 4-to-16 line decoder/demultiplexer, inverting outputs |
| 15. | 74HCT157 | 1 | Quad 2-line to 1-line data selector/multiplexer, non-inverting outputs |
| 16. | 74HCT163 | 5 | Synchronous presettable 4-bit binary counter, synchronous clear |
| 17. | 74HCT173 | 27 | Quad D flip-flop, asynchronous clear |
| 18. | 74HCT181 | 2 | 4-bit arithmetic logic unit and function generator |
| 19. | 74HCT193 | 2 | Synchronous presettable up/down 4-bit binary counter |
| 20. | 74HCT244 | 20 | Octal buffer, non-inverting outputs |
| 21. | MCP100-475DI | 2 | 4.75V supervisory circuit |
| 22. | AT28C256-15PU | 3 | 32k x 8bit parallel EEPROM |
| 23. | AS6C62256-55P | 2 | 32k x 8bit parallel SRAM |
| 24. | Female 2x4 pin header 2.54mm | 2 | |
| 25. | Female 2x3 pin header 2.54mm | 1 |