XiPU - Simulation of the processor
Overview of the processor simulation. What tool is used for simulation. Full description how to configure and run the processor in the virtual environment.
1. Tool
For simulation has been used Proteus 8 Professional. With that tool is possible to use a full family of TTL 7400 chips in the virtual environment. It is possible to run the processor in real time speed or in step by step mode for debugging.
Testing and looking for bugs is much easier than doing it with real parts on the desk. It supports checking logic levels on wires, buses and shows any bad logic cases in the event log. Every chip has fully simulated its behavior and delays on outputs.
2. Configuration
To run the simulation two uROM files and one file with a program are needed. In practice the file with the program is used for Operating System but in simulation mode it is better to run a much simplest programs for testing purposes. The uROM files and the simple program can be found in download section of this page.
Before first run you need to add image files to the chips on simulation:
1. Go to "Design" -> "3. I, CU"
2. Right click on "uROM #0" and select from the context menu "Edit Properties"
3. In the "Image File" field set a destination to the "urom0.bin" file and click "OK"
4. Do it again with "uROM #1" and set a destination to the "urom1.bin" file.
5. Go to "Design" -> "4. FLASH, SRAM"
6. Right click on "32K Flash memory" and select from the context menu "Edit Properties"
7. In the "Image File" field set a destination to the "rom.bin" file and click "OK"
8. You can start now the simulation by clicking the "play" button on the left bottom corner of the application window.
3. Debug Interface
On the debug interface page you can see current status of all registers and buses of the processor. On the left bottom corner are 8 switches using for manual controlling the Input Register.
3.1. Clock and instruction register
| Name | Description |
|---|---|
| CLK | Clock used to selecting a step from uROM for the current executing instruction. Its maximum value is 15 and it is always reset at the end of the instruction. |
| I | Current executing instruction opcode. |
3.2. Buses
| Name | Description |
|---|---|
| BUS AR | Input selector for the main data bus. List of possible sources: 0x0 : ABXY - Main and auxiliary registers |
| BUS AW | Output selector for the main data bus. List of possible destinations: 0x0 : None - Not selected |
| BUS B | Input selector for the auxiliary data bus. List of possible sources: 0x0 : AB - Main registers |
| BUS C | Input selector for memory address bus. List of possible sources: 0x0 : PC - Full 16 bit Program Counter register |
3.3. Memory address registers
| Name | Description |
|---|---|
| PCH:PCL | Program Counter. |
| SPH:SPL | Stack Pointer. |
| MAH:MAL | Memory Address. |
3.4. Registers
| Name | Description |
|---|---|
| A | Main Accumulator Register. |
| B | Auxiliary Accumulator Register. |
| X | Low Addressing Register. |
| Y | High Addressing Register. |
3.5. IO Registers
On the left side are 8 switches to manually change the value of the Input Register.
| Name | Description |
|---|---|
| IN | Input Register. |
| OUT | Output Register. |
3.6. Buffer registers
| Name | Description |
|---|---|
| ALU | Operation selector for the Arithmetic Logic Unit. List of possible operations: 0x00 : Out = In_A + 1 |
| T | ALU output buffer. |
| CZ | ALU flags buffer. List of used bits: 0x1 - Carry Flag. The logic of the Carry Flag is inverted in this CPU. |