Simulation of the processor

30.07.2021

Overview of the processor simulation. What tool is used for simulation. Full description how to configure and run the processor in the virtual environment.

1. Tool

For simulation has been used Proteus 8 Professional. With that tool is possible to use a full family of TTL 7400 chips in the virtual environment. It is possible to run the processor in real time speed or in step by step mode for debugging.

Testing and looking for bugs is much easier than doing it with real parts on the desk. It supports checking logic levels on wires, buses and shows any bad logic cases in the event log. Every chip has fully simulated its behavior and delays on outputs.

2. Configuration

To run the simulation two uROM files and one file with a program are needed. In practice the file with the program is used for Operating System but in simulation mode it is better to run a much simplest programs for testing purposes. The uROM files and the simple program can be found in download section of this page.

Before first run you need to add image files to the chips on simulation:
1. Go to "Design" -> "3. I, CU"

Design menu

2. Right click on "uROM #0" and select from the context menu "Edit Properties"

uRom 0

3. In the "Image File" field set a destination to the "urom0.bin" file and click "OK"

Edit Component

4. Do it again with "uROM #1" and set a destination to the "urom1.bin" file.
5. Go to "Design" -> "4. FLASH, SRAM"
6. Right click on "32K Flash memory" and select from the context menu "Edit Properties"

ROM

7. In the "Image File" field set a destination to the "rom.bin" file and click "OK"
8. You can start now the simulation by clicking the "play" button on the left bottom corner of the application window.

Control Menu

3. Debug Interface

On the debug interface page you can see current status of all registers and buses of the processor. On the left bottom corner are 8 switches using for manual controlling the Input Register.

Debug Interface

3.1. Clock and instruction register

Name Description
CLK Clock used to selecting a step from uROM for the current executing instruction. Its maximum value is 15 and it is always reset at the end of the instruction.
I Current executing instruction opcode.

3.2. Buses

Name Description
BUS AR Input selector for the main data bus. List of possible sources:
0x0 : ABXY - Main and auxiliary registers
0x1 : D - Hidden data register
0x2 : IN - Input register
0x3 : T - ALU temp register
0x4 : Ram - RAM access
0x5 : Flash - FLASH access
0x6 : PCL - Program Counter Low register
0x7 : PCH - Program Counter High register
BUS AW Output selector for the main data bus. List of possible destinations:
0x0 : None - Not selected
0x1 : ABXY - Main and auxiliary registers
0x2 : D - Hidden data register
0x3 : OUT - Output register
0x4 : ALU_T - ALU operation
0x5 : RPC - Reset Program Counter
0x6 : I - Instruction register
0x7 : Ram - RAM access
0x8 : PCL - Program Counter Low register
0x9 : PCH - Program Counter High register
0xA : MAL - Memory Address Low register
0xB : MAH - Memory Address High register
0xC : PC_PLUS - Increse Program Counter
0xD : SP_PLUS - Increse Stack Pointer
0xE : SP_MINUS - Decrese Stack Pointer
0xF : RPC_PLUS - Reset the step counter and increse Program Counter
BUS B Input selector for the auxiliary data bus. List of possible sources:
0x0 : AB - Main registers
0x1 : D - Hidden data register
BUS C Input selector for memory address bus. List of possible sources:
PC - Full 16 bit Program Counter register
MA - Full 16 bit Memory Address register
SP - Full 16 bit Stack Pointer register
XY - Full 16 bit auxiliary register

3.3. Memory address registers

Name Description
PCH:PCL Program Counter.
SPH:SPL Stack Pointer.
MAH:MAL Memory Address.

3.4. Registers

Name Description
A Main Accumulator Register.
B Auxiliary Accumulator Register.
X Low Addressing Register.
Y High Addressing Register.

3.5. IO Registers

IO Registers

On the left side are 8 switches to manually change the value of the Input Register.

Name Description
IN Input Register.
OUT Output Register.

3.6. Buffer registers

Name Description
ALU Operation selector for the Arithmetic Logic Unit. List of possible operations:
0x00 : Out = In_A + 1
0x03 : Out = 0
0x06 : Out = In_A - In_B
0x09 : Out = In_A + In_B + 1
0x0C : Out = In_A + In_A + 1
0x0F : Out = In_A
0x10 : Out = NOT In_A
0x16 : Out = In_A XOR In_B
0x1B : Out = In_A AND In_B
0x1E : Out = In_A OR In_B
0x20 : Out = In_A
0x26 : Out = In_A - In_B - 1
0x29 : Out = In_A + In_B
0x2C : Out = In_A + In_A
0x2F : Out = In_A - 1
T ALU output buffer.
CZ ALU flags buffer. List of used bits:
0x1 - Carry Flag. The logic of the Carry Flag is inverted in this CPU.
0x2 - Zero Flag

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