Architecture of the processor


Description of the XiPU processor architecture. A quick overview how everything is connected, how many registers the processor has, how buses connects all blocks together and how it works in bigger perspective.

1. The XiPU Connection Diagram

The XiPU Connection Diagram

2. Memory structure

ROM and RAM share the same address and data buses. Both memory types has 64 KB address spaces and access to them is realized by two different instruction set. The Control Unit selects the memory chip which is currently in use.

The ROM memory is used only for storing an executable code and constants variables. It is possible only to execute an instruction or read data. Writing to this memory is not supported.

The RAM memory is used only for storing variables. It is possible to read and write. The memory is not cleaned at start.

The address space of the memory is a hybrid. The lower 32 KB ROM and RAM addresses are separated. The higher 32 KB of both memories in real are stored in RAM and it is virtual mirrored to the ROM address space. The higher memory is used for loading and running applications from an external storage.

Memory structure

2.1. ROM

Address ranges:

Start End Size Description
0x0000 0x7FFF 32 KB It is used by the Operating System burned into the EEPROM chip.
0x8000 0xFFFF 32 KB It is used for applications. It is virtually mirrored from the same RAM address space.

Start addresses:

Address Description
0x0000 The reset start address for the processor. It used to startup the Operating System.
0x8000 Start address for an application.

2.2. RAM

Address ranges:

Start End Size Description
0x0000 0x0EFF 3840 bytes Operating System space for variables.
0x0F00 0x0FFF 256 bytes Address space used by the stack.
0x1000 0x7FFF 28 KB Address space used by an application for variables and temporary data.
0x8000 0xFFFF 32 KB Address space used to load an executable code of the application. It is accessible from the same ROM address space by virtual mirroring.

3. Buses

List of buses:

Name Width Description
BUS A 8 bits Main read-write data bus. Using for transfer data between registers and memory. The source of the first argument and output for the Arithmetic Logic Unit.
BUS B 8 bits Auxiliary write-only data bus. The source of the second argument for the Arithmetic Logic Unit.
BUS C 16 bits Write-only addressing bus. Using for memory addressing.

4. Registers

4.1. General Purpose Registers

Registers accessible directly from the assembler code. They can be used as source or destination for data. They can be used as the input and the output for ALU.

Name Width Description
A 8 bits Main Accumulator Register.
B 8 bits Auxiliary Accumulator Register.
Y : X 16 bits Addressing pair of registers. It can be used as two 8 bits auxiliary registers. They cannot be used as the second argument for the ALU.

4.2. Hidden Registers

Registers not accessible from the assembler code but used in the decoding process of the current instruction.

Name Width Description
I 8 bits Instruction Register. It contains a current decoding and executing instruction by the processor.
D 8 bits Hidden Temporary Data Register. It is used by the processor as a place for save for a while data needed in next steps of decoding the current instruction.
PCH : PCL 16 bits Program Counter. Pair of registers used to address the next instruction to load from ROM.
MAH : MAL 16 bits Memory Address. Pair of registers used to address destination or source in ROM and RAM for storing or loading data.
SPH : SPL 16 bits Stack Pointer. Pair of registers used to address the head of the stack. SPH is hardware fixed to 0x0F value. It means that the stack size is 256 bytes.

4.3. Buffer Registers

Registers used as buffers for ALU operations.

Name Width Description
C 1 bit Carry Flag. ALU output used in comparing two values. The logic of the Carry Flag is inverted in this CPU.
Z 1 bit Zero Flag. ALU output used in comparing two values.
T 8 bits Temporary ALU Output Register. It is used to buffer ALU output before writing it to the destination register.

4.4. IO Registers

Registers used for communication to the motherboard. They create a simple external data bus.

Name Width Description
IN 8 bits Input Register. It is used to read data from the incoming bus.
OUT 8 bits Output Register. It is used to write data to the outgoing bus.

5. Arithmetic Logic Unit

ALU has two 8 bit inputs and one 8 bit output. It can add, subtract, shift and make basic logic operations. It can compare two values and the output status of the Carry and the Zero flags can be used for the conditional jump and loop.

6. Control Unit

It steers whole CPU. It decodes every instruction and executes micro steps based on uROM. CU responses which register or memory is selected to read and write.

7. Stack

Direct access to the Stack Registers is not possible. It is only possible to push and pop a register on the stack. It can be used to store a return address for the calling function. The size of the stack is 256 bytes. 2021-2022 © All rights reserved